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Title:
PULSE GENERATING CIRCUIT
Document Type and Number:
Japanese Patent JPS5446411
Kind Code:
A
Abstract:

PURPOSE: To make it possible to generate the initial reset or start pulse of an apparatus, which synchronizes with the 1st pulse of an input pulse of constant frequency, without delay by using a N number of cascaded monostable multivibrators.

CONSTITUTION: Monostable multivibrator 14 is triggered at the leading edge of an input pulse, monostable multivibrator 15 is triggered at the trailing edge of its output pulse, and monostable multivibrator 16 is triggered at the trailing edge of its output pulse. Then, the operation output of monostable multivibrator 14 and the non-operation output of monostable multivibrator 16 are supplied to NAND circuit 17, whose output is used as the reset pulse of digital apparatus 13; and then, operation outputs of monostable multivibrators 14 to 16 are inputted to OR circuit 18, whose output is applied to apparatus 13 as a start pulse after charging capacitor 19 giving a fixed time lag. Consequently, a reset pulse or start pulse can be generated without delay even if the period of an input pulse fluctuates


Inventors:
ISHIMARU NOBUYUKI
Application Number:
JP11376977A
Publication Date:
April 12, 1979
Filing Date:
September 20, 1977
Export Citation:
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Assignee:
HITACHI ELECTRONICS
International Classes:
H04N5/08; H04N5/06; H04N5/12; (IPC1-7): H04N5/06; H04N5/12



 
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