PURPOSE: To obtain a pulse generating circuit with uniform pulse width which suits to integration, by controlling the conduction of the logical circuit, composed of two transfer gates, an inverting circuit, and an NOR gate, by a couple of synchronizing pulses which have complementary relation.

CONSTITUTION: When an input signal IN is at a level 1, an MOS transistor TR21 turns on at the timing of a clock pulse - and turns off at the timing of a clock . Therefore, the output signal A of the TR21 holds the level 1 of the signal IN statically during a period of the -, and a floating capacitance 25 holds it dynamically during a period of the to obtain the 0-level output signal B of an MOS inverter IV22. A TR23 turns on during a period of the clock and turns off during a period of the -. Therefore, the output signal C of the TR23 holds the level 0 of a signal B statically during a period of the clock and a floating capacitance 26 holds it dynamically during a period of the clock -. Therefore, an NOR gate 24 outputs a pulse OUT having pulse width which corresponds to one bit of the clock pulses.