PURPOSE: To generate pulses at a high speed by storing the 1st data to be set in a counter and the 2nd data to be applied to a delay circuit in the same addresses of respective memories previously.

CONSTITUTION: The counter 5 is a counter which divides an input signal by (m) and sends its output to an address counter 6, a shift register 8, and a shift register 9 every time it counts the output of a detecting circuit 2 up to (m). An address counter 6, on the other hand, updates its counted value by +1 every time it counts the output of the counter 5 and also sends its output to the address terminal of a memory 7. The memory 7 is stored with the 1st data to be set in a counter 1 and the 2nd data for selecting the delay time of the delay circuit 4 by (m) pieces each in the same address. Then, necessary data are read out the memory 7 into the shift registers 8 and 9, so a high-speed pulse signal is generated within the operation range of the shift registers 8 and 9.