Title:
PULSE GENERATION CIRCUIT, SAMPLE-AND-HOLD CIRCUIT AND SOLID STATE IMAGING DEVICE
Document Type and Number:
Japanese Patent JP2014180006
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a pulse edge selection circuit that cuts down power consumption by reducing logic gates driven and shortens clock delay by reducing the number of logic gates through which clocks pass, and a pulse generation circuit, sample-and-hold circuit and solid state imaging device therewith.SOLUTION: The pulse edge selection circuit has input stages each for selecting and passing one clock from a plurality of clocks, and output stages each for outputting the one clock to an edge detection circuit. In the case of an edge detection circuit configured to detect fall edges of the clocks and generate a pulse which rises on the fall edge of a first one of the clocks and falls on the fall edge of a second one of the clocks, the output stages comprise alternately combined connections of a plurality of NOR gates having a plurality of input ends and a plurality of NAND gates having a plurality of input ends, and NOR gates are used as output gates for outputting the first and second clocks. In the case of generating a pulse on rise edges, NAND gates are used as the output gates.
Inventors:
IWANE MASAAKI
Application Number:
JP2014090473A
Publication Date:
September 25, 2014
Filing Date:
April 24, 2014
Export Citation:
Assignee:
CANON KK
International Classes:
H03K5/135; H03K5/08; H03K5/15; H03K5/1534; H03L7/08
Domestic Patent References:
| JPS62176320A | 1987-08-03 | |||
| JPH07202652A | 1995-08-04 | |||
| JPH0851346A | 1996-02-20 | |||
| JP2008125046A | 2008-05-29 | |||
| JP2009206709A | 2009-09-10 |
Attorney, Agent or Firm:
Yasunari Otsuka
Shiro Takayanagi
Yasuhiro Otsuka
Hideji Kimura
Shimoyama 治
Yukimitsu Nagagawa
Shiro Takayanagi
Yasuhiro Otsuka
Hideji Kimura
Shimoyama 治
Yukimitsu Nagagawa