To provide a generation circuit width eliminates the need for the interruption processing into a CPU and for large memory space and generate the pulse signal at an arbitrary frequency.

A preliminarily set number of steps frequency division is performed for a reference clock signal Fc by a frequency divider circuit 1, the signal is outputted, a basic clock signal Fb to be the output of the frequency divider circuit 1 is inputted in an acceleration-deceleration circuit and the output signal Fout to be the pulse signal that the basic clock Fb is further frequency- divided by the acceleration-deceleration circuit 2 is outputted. The frequency of the output signal Fout of the acceleration-deceleration circuit 2 changes based on the data which is set to a data register control part 3 and is inputted. The data register control part 3 fetches the data Sc set in an initial value register 6 as the data for determining a starting frequency. Subsequently, when the addition/subtraction request signal Sr is received from a timing generation circuit 7, the arithmetic result as read by an adder-subtracter 4.