To provide a driving circuit of a display device composed of semiconductor TFTs and obtaining a proper amplitude of an output signal.
The TFTs 101, 104 are turned ON by an input of a pulse thereto. After a potential of a node is increased, they are floated at VDD-VthN. The TFT 105 is turned ON and the potential of an output node is increased as a clock signal becomes Hi. On the other hand, a potential of a gate electrode of the TFT 105 is further increased by an operation of a capacitance 107 as a potential of the output node increases beyond VDD+VthN. The potential of the output node is increased up to VDD without causing a voltage drop by the threshold of the TFT 105. After that, the TFTs 102, 103 are turned ON by an input of a next stage output thereto, and the potential of the node drops to turn OFF the TFT 105. Simultaneously, the TFT 106 is turned ON and the potential of the output node becomes Lo.
| JP2023130388 | LIQUID CRYSTAL DISPLAY |
| JP3742067 | DRIVING CIRCUIT AND ACTIVE MATRIX PANEL |
NAGAO SHO
TANADA YOSHIFUMI
| JP2001060398A | 2001-03-06 | |||
| JPS5693431A | 1981-07-29 | |||
| JP2001101889A | 2001-04-13 | |||
| JPH03163911A | 1991-07-15 | |||
| JPS5248458A | 1977-04-18 |
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