Title:
PULSE SIGNAL OUTPUT CIRCUIT AND SHIFT REGISTER
Document Type and Number:
Japanese Patent JP2011205630
Kind Code:
A
Abstract:
To provide a pulse signal output circuit that operates stably and a shift register including the pulse signal output circuit.
The pulse signal output circuit includes a first to tenth transistors. The ratio W/L of the channel width W to the channel length L of the first transistor and W/L of the third transistor are each larger than W/L of the sixth transistor. W/L of the fifth transistor is larger than W/L of the sixth transistor. W/L of the fifth transistor is equal to W/L of the seventh transistor. W/L of the third transistor is larger than W/L of the fourth transistor. With such a structure, a pulse signal output circuit that operates stably and a shift register including the pulse signal output circuit can be provided.
More Like This:
JP5346259 | Semiconductor integrated circuit |
JP2013229902 | SEMICONDUCTOR DEVICE |
JPH0752832 | [Title of Invention] Input circuit |
Inventors:
AMANO KIYOKO
TOYOTAKA KOHEI
MIYAKE HIROYUKI
MIYAZAKI AYA
SHISHIDO HIDEAKI
KUSUNOKI KOJI
TOYOTAKA KOHEI
MIYAKE HIROYUKI
MIYAZAKI AYA
SHISHIDO HIDEAKI
KUSUNOKI KOJI
Application Number:
JP2011045420A
Publication Date:
October 13, 2011
Filing Date:
March 02, 2011
Export Citation:
Assignee:
SEMICONDUCTOR ENERGY LAB CO LTD
International Classes:
H03K19/0175; G11C19/00; H01L29/786; H03K19/096; H03K23/54
Domestic Patent References:
JP2008122939A | 2008-05-29 | |||
JP2008281671A | 2008-11-20 | |||
JP2005037842A | 2005-02-10 | |||
JP2008107807A | 2008-05-08 | |||
JP2011030171A | 2011-02-10 |
Previous Patent: IMAGE FORMING APPARATUS AND IMAGE FORMING METHOD
Next Patent: SUPER-RESOLUTION BLIND CHANNEL MODELING METHOD
Next Patent: SUPER-RESOLUTION BLIND CHANNEL MODELING METHOD