To provide a pulse width modulation circuit that can solve the problem in which, at a transition to a power-off state, leakage currents charging storage means bring both inputs of two output elements to a high level and both outputs thereof to a low level to disable a pulse width modulation operation from starting up at a subsequent transition to a power-on state, and that can output pulse width modulation signals accurately corresponding to an input signal.
A pulse width modulation circuit 20 includes switch means Q4 that, at a transition from a power-on state to a power-off state, is controlled to an on state to instantaneously discharge a supply voltage VB causative of leakage currents to a ground potential until it becomes 0 V. The switch means Q4 is connected to each cathode side of diodes D1, D2, and is electrically isolated from capacitors C1, C2 when currents I1, I2 charge the capacitors C1, C2 to keep from causing errors in charging C1, C2.
MINAGAWA ATSUSHI
UMETSU NORIO
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