PURPOSE: To reduce power consumption at a low power consumption mode by fixing the output of a data addition circuit constant when all N bits of data values set in a data register are '1'.

CONSTITUTION: A '1' detection circuit 44 outputs '1' when the bits of the data values set in the data register 43 are all '1', and '0' in another case, to an output control circuit 45. The output control circuit 45 is an OR circuit, namely, it outputs a data addition/output S-46 being one input signal as it is when an input signal S-45 is '0' and outputs '1' in spite of the value of the pulse width modulation output S-46 when the input signal S-45 is '1'. Thus, the power consumption of a system can be reduced by fixing a pulse width modulation output constant since the data detection circuit 45 of the data register 43 controls the pulse width modulation output.