To provide a pulse width modulator that has an increased dynamic range by implementing an increased resolution.
The pulse width modulator includes: a sequence counter 24 for counting a count value in synchronism with a clock; an intermediate register processing section 20 for changing a pulse width chronologically symmetrically with respect to a change time point of the switching period of an input signal by reference to the counter value from the sequence counter if the input signal is a first input signal pattern type or changing the pulse width one clock longer on the earlier or later side of the change time point of the switching period of the input signal by reference to the counter value from the sequence counter if the input signal is a second input signal pattern type, and outputting corresponding intermediate register values; and a decoder 22 for generating an output signal based on the intermediate register values from the intermediate register processing section by reference to the counter value from the sequence counter.
JP2004032095A | 2004-01-29 | |||
JP2009525642A | 2009-07-09 | |||
JP2004357450A | 2004-12-16 | |||
JP2005341568A | 2005-12-08 | |||
JP2005277818A | 2005-10-06 |
Keishin Terayama
Hiroyuki Miyoshi
Ichitaro Ito