To provide a pulse width signal converting circuit which can surely uniformly convert pulse width signals.

In converting PWM signals Di into parallel digital data, a pulse width signal converting circuit detects the rising edge of the signals Di by means of an edge detecting circuit 102, synchronizes a clock CLK for conversion with the edge detecting timing by means of a gate 103, and outputs a clock SCK for counting by delaying the clock SCK by a prescribed period of time by means of a delay circuit 104. Then the conversion circuit counts up or count down the PWM signals Di by using the clock SCK for counting by resetting an up/down counter 101 at the edge detecting timing.