To provide a digital input PWM power amplifier which is operated with high efficiency and by a comparatively low switching frequency.
This digital input PWM power amplifier is provided with an over-sampling noise shaping circuit, a first bus for transmitting the maximum digit bit (most significant bit) of a first number D, the second bus for transmitting the minimum digit bit (least significant bit) of the second number S and first and second PCM/PWM converters for respectively receiving the supply of first and second number bits and outputting PWM signals (MSBdig and LSBdig). The PWM signal(MSBdig) outputted by the first converter is added to the PWMsignal(LSBdig) outputted by the second one on the reverse input node(-) of an output power stage.
GROSSO ANTONIO