To provide a PWM signal generating circuit reduced in power consumption and high in accuracy.

A counter 2 generates a pulse width of integral times as large as one period of a clock signal according to the upper bit of a digital input signal DIN. A slope wave generator 4 generates slope waves after the generation of the pulse width of integral times. A peak detector 5 generates a reference voltage VREF corresponding to peak values of the slope waves. A D-A converter 6 generates an analog output voltage specified by the lower bit of the digital input signal DIN at a voltage level lower than or equal to the reference voltage while using the reference voltage as a full-scale voltage. An analog comparator 7 detects the crossing timing of the analog output voltage and the slope waves. A digital output circuit 8 outputs a pulse-width modulation output signal PWMOUT having an output pulse width obtained by adding the pulse width of integral times and the crossing timing.