Title:
QAM MAPPING DEVICE AND MAPPING METHOD
Document Type and Number:
Japanese Patent JP2016059056
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To reduce a bit error rate in a QAM scheme.SOLUTION: A QAM mapping device 13 for modulating data by QAM uses a mapping pattern in which bits of an upper-level side (MSB side) of a symbol are allocated to a synchronization signal per quadrant of an IQ plane representing a position of a symbol and performs synchronization processing only by the upper-level side bits. The QAM mapping device uses a mapping pattern in which bits of lower-level side (LSB side) of the same symbol are allocated to symbols adjacent across an I axis or a Q axis in between, and reduces a bit error rate at a time of determination occurring when distance between symbols in different quadrants is short.SELECTED DRAWING: Figure 3
Inventors:
HOSOYA HIDEKAZU
YAMAZAKI ETSUSHI
KISAKA YOSHIAKI
YONENAGA KAZUSHIGE
KATAOKA TOMOYOSHI
YAMAZAKI ETSUSHI
KISAKA YOSHIAKI
YONENAGA KAZUSHIGE
KATAOKA TOMOYOSHI
Application Number:
JP2015224415A
Publication Date:
April 21, 2016
Filing Date:
November 17, 2015
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H04L27/36
Domestic Patent References:
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| JP2011083030A | 2011-04-21 | |||
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Attorney, Agent or Firm:
Yoshimoto Toyoda
Hiroshi Watanabe
Hiroshi Watanabe