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Title:
QUADRATURE DETECTOR
Document Type and Number:
Japanese Patent JPS6042906
Kind Code:
A
Abstract:

PURPOSE: To obtain a quadrature circuit with simple adjustment and less distortion by adding a distortion cancellation circuit to a single tuning circuit.

CONSTITUTION: An output of a multiplier 3 is given to one input of an adder 9, both inputs of a multiplier 6 and one input of a multiplier 7. The output of the multiplier 6 is given to the other input of the multiplier 7 and the output of the multiplier 7 is given to the input of an attenuator 8. Further, the output of the attenuator 8 is given to the other input of an adder 9 and the output of the adder 9 becomes a detected output 4. A square term of the output of the multiplier 3 is obtained at the output of the multiplier 6. Since the fundamental and the square term of the fundamental wave are applied to the input of the multiplier 7, a cube term of the fundamental wave is obtained at the output. Thus, a waveform from which the 3rd harmonic is cancelled is obtained by subtracting the cube term from the output of the multiplier 3 by means of the adder 9.


Inventors:
OOTAKI KIYOSHI
ISHIDA KOUJI
Application Number:
JP15136683A
Publication Date:
March 07, 1985
Filing Date:
August 19, 1983
Export Citation:
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Assignee:
PIONEER ELECTRONIC CORP
International Classes:
H03D3/00; H03D3/06; (IPC1-7): H03D3/00
Domestic Patent References:
JPS5272512A1977-06-17