To realize a system in which a timing constraint associated with performing inter-symbol interference reduction is relaxed.
A system for relaxing a timing constraint associated with reducing inter-symbol interference (ISI) of input data comprises: a speculative analog circuit configured to receive input data at a first clock rate, add an inter-symbol interference (ISI) cancellation value to the input data to generate first speculative data, and subtract the inter-symbol interference cancellation value from the input data to generate second speculative data; and a sampling circuit communicatively coupled to the speculative analog circuit and configured to sample the first speculative data and the second speculative data at a second clock rate that is one-fourth of the first clock rate such that a timing constraint associated with performing the inter-symbol interference reduction is relaxed.
| JP2011244284A | 2011-12-01 |
| US20080187036A1 | 2008-08-07 | |||
| US20090252215A1 | 2009-10-08 | |||
| US20110096825A1 | 2011-04-28 |
Koichi Itsubo
Higuchi Souji