PURPOSE: To shorten the access processing time of a queue for communication and to simplify its control by changing the queue for communication between processors from the chain system to the ring buffer system.
CONSTITUTION: A memory shared between processors 10 and 20 is provided with queues 30 and 40 for communication in the ring buffer system, and queues for communication between processors are controlled. In this case, queues for communication between processors 10 and 20 consist of a read pointer 101 for reception, a write pointer 102 for transmission, and resources 201 to 206 for communication. When transmitting data to the processor 10, the processor 20 writes the number of the resource in the pointer pointed by the write pointer 102 of the queue 30 for communication of a queue control mechanism part 60 and updates the pointer. The processor 10 on the reception side takes out the resource number from the pointer pointed by the read pointer 101 of the queue 30 for communication of a queue control mechanism part 50 and updates the pointer.
JP2020198044 | PARALLEL PROCESSING DEVICE |
JPH04326151 | BUFFER CONTROL CIRCUIT |