PURPOSE: To make the write pulse width freely changeable by using the front- edge pulse width of a clock input as the write pulse width when the front-edge pulse width is larger than the pulse width which assures the minimum width of the write pulse width.

CONSTITUTION: A write instructing input inputted from an input 41 makes a write pulse effective at the time of writing operations. Clock inputs inputted from another input 42 are passed through a delay line 51 and one side of the inputs is inputted to a write pulse switching section 53. The other part is inputted to a delay line 52 which produces the minimum width of the write pulse width and the output of the line 52 is inputted to the switching section 53. When the front-edge pulse width of the clock inputs is larger than the pulse width of the line 52 which produces the minimum pulse width, the front-edge pulse width is used as the write pulse width at the switching section 53. When the front-edge pulse width is smaller, on the other hand, the pulse width of the line 52 is outputted for assuring the minimum write pulse width for writing in a RAM cell array.