To realize a low power consumption and a high speed readout of a random access memory.

Prior to readout, global bit lines GB1, GB2 shared by a plurality of memory blocks MB1 to MBn and local bit lines LB1, LB2 shared by memory cells M1 to Mn in the memory blocks are connected to precharge circuits 10, 50 for precharging the global bit lines GB1, GB2 and all of the local bit lines LB1, LB2. At the time of the readout, the global bit lines GB1, GB2 and the local bit lines LB1, LB2 of the blocks having the memory cells to be accessed are connected. Furthermore, transistors 41, 42 are provided for connecting the global bit lines GB1, GB2 and all of the local bit lines LB1, LB2 prior to the readout.