RANDOM NUMBER GENERATION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT

Title:

RANDOM NUMBER GENERATION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT

Document Type and Number:

Japanese Patent JP2006189946

Kind Code:

A

Abstract:

To provide a random number generation circuit and a semiconductor integrated circuit capable of realizing speedup and reduction in size at the same time.

This random number generation circuit 1 is provided with a noise generation source 2 generating a noise signal, a filter 3 extracting a part of a frequency band of the noise signal, and a comparator 4 amplifying a signal difference between a part of the noise signal frequency band and a reference signal for generating a random number signal. The random number generation circuit 1 is installed on a base board for the semiconductor integrated circuit.

Inventors:

YASUDA SHINICHI
FUJITA SHINOBU

Application Number:

JP2004381849A

Publication Date:

July 20, 2006

Filing Date:

December 28, 2004

Export Citation:

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Assignee:

TOSHIBA CORP

International Classes:

G06F7/58; G09C1/00; H03K3/84

Attorney, Agent or Firm:

Hidekazu Miyoshi
Iwa Saki Kokuni
Kawamata Sumio
Nakamura Tomoyuki
Masakazu Ito
Shunichi Takahashi
Toshio Takamatsu

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