PURPOSE: To realize generation of a maximum cycle train of a desired cycle by outputting a shift clock signal to a maximum cycle generating means for each first external operation and erasing the stored contents with a second external operation for generation of a new maximum cycle train.
CONSTITUTION: A control circuit 20 inputs a start signal ST to a calculator 19 after the release of a reset state. When an output control signal OC is applied to an S/P converter 16 via an operation control part 23, the stored contents and outputted to a data bus 17. A control circuit 22 outputs the clock signals to the clock input terminals CK of shift registers 12 and 13 for each application of these signal IC. When the first clock is outputted, the register 13 delivers the data 1 or 0 to an output line 15. Then the data 1 or 0 is stored in the converter 16. The circuit 20 outputs the clock signals to a clock line 21 every time the part 23 reads out the stored contents of the converter 16. Thus it is possible to avoid such a case where the periodicity of a produced random number becomes conspicuous.
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NAGANO TAKESHI
NAGAMI MASAAKI
FUJIMOTO SHOJI
YASUI KATSUMARO
