PURPOSE: To realize the circuit to convert a low-speed transmitting encoding signal to a high-speed convolution encoding signal with simple circuit configuration so as to input the convolution encoding signal to a viterbi decoder.

CONSTITUTION: A clock generator 2 is provided to generate the N (N is an integer number larger than 2) fold clock of a system clock used for the transmission line. of TDMA communication or the like, and one timing generator 3 is provided to generate the system clock by dividing the frequency of this N fold clock and to output the system clock and the N fold clock. Then, a buffer memory 5 is provided to read a receiving bus data with the N fold clock after writing the data in a memory and buffering it by the system clock.