To provide a re-timing circuit and a frequency dividing system capable of preventing malfunction when the timing of a synchronous edge in a clock signal coincides with that of an edge in an input signal.

The re-timing circuit including a first flip-flop circuit 102 that inputs a differential clock signal in first and second clock terminals, inputs a first differential signal in first and second input terminals, and outputs a second differential signal from first and second output terminals, an inphase detecting circuit 105 that outputs an inphase detecting signal if the first and second signals constituting the second differential signal become inphase, a counter 106 that counts a count value of the inphase detecting signal, and a switching selector 101 that switches a phase of the differential clock signal that is input in the first and second clock terminals in the first flip-flop circuit is provided.