PURPOSE: To improve the data reading speed by applying a read voltage to a drain line, and precharging a gate line and then reading held data out of a semiconductor memory element when the data held in the semiconductor memory element is read.

CONSTITUTION: Memory elements M1 - M8 are provided at respective intersections of gate lines G1 and G2 and drain lines D1 - D4 which are arranged in matrix, and the drain lines D1 - D4 are applied with the read voltage V+ through MOS transistors(TR) 11 - 14. Then the gate lines G1 and G2 are precharged with gate line select signals GA1 and GA2 and after data of memory elements M1 - M4, and M5 - M8 are determined, the data are read out. Consequently, data read signals CA1 - CA4 need not be give time width for charging-up operation and the data read speed is improved.