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Patent Searching and Data


Title:
REBIAS DEVICE IN SPEED CONVERTER USING MEMORY
Document Type and Number:
Japanese Patent JPH0282832
Kind Code:
A
Abstract:

PURPOSE: To avoid the collision of both a write control signal and a readout control signal even if the accuracy of timing control of the write control signal of the readout control signal is comparatively deteriorated by colliding the write control signal and the readout control signal forcedly at system rising or the like.

CONSTITUTION: The collision is forcedly caused at system rising and a collision detection section 15 in a collision control section 25 detects the collision. When the collision is detected, since a FF 12 is reset in a timing t9 of a detection signal DET rising from a low level to a high level, the phase of read reset signals RRI*, RRII* is shifted by a half period with respect to the phase of write reset signals WRI* and WRII* by a half period, and the collision between the write reset signal WRI* and the read reset signal RRI* and the collision between the write reset signal WRII* and the read reset signal PRII* are avoided.


Inventors:
FUKUYAMA AKIFUMI
TANAKA SHINJI
OSAKI KIMIYA
Application Number:
JP23350888A
Publication Date:
March 23, 1990
Filing Date:
September 20, 1988
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F5/12; G06F5/06; H04L7/00; H04L13/08; (IPC1-7): G06F5/06; H04L7/00; H04L13/08
Attorney, Agent or Firm:
Yoshiyuki Osuge (1 outside)