PURPOSE: To prevent defect of transfer due to missing of a transmission data or the like regardless of a rapid frequency change of a received line clock signal when a received data is stored tentatively in a buffer memory and sent to a device system with a system clock signal.

CONSTITUTION: When an input data received from a communication network 20 is tentatively stored in a buffer memory 12 and the data having been stored precedingly is sequentially extracted, a phase comparator section 14 compares the phase and speed (frequency) of a line clock signal received from the communication network 20 with those of the system clock signal of the device system 30 and outputs a difference, and a feedback quantity arithmetic section 15 calculates a feedback quantity to vary the difference gradually and automatically according to a prescribed arithmetic equation such as hyperbolic tangent tanh(f) of a frequency change f depending the outputted difference and an output timing adjustment section 16 adjusts the timing of extracting the output data according to the calculated value and extracts the result one by one.