To provide a receiver provided with a threshold value setting means capable of measuring the amplitude of a received signal and more properly setting a required threshold to a comparator.
The receiver is constituted of: a detection means 104 for detecting the received signal; a sampling clock generating means 103 for generating a sampling clock on the basis of an output of the detection means 104; a detection output sampling means 105 for sampling an output of the detection means 104 in the timing of an output of the sampling clock generating means 103; and an arithmetic means 106 for setting a threshold of a discrimination means 107 that discriminates the output of the detection means 104 on the basis of an output of the detection output sampling means 105, and the receiver sets the threshold required for particularizing received data adopting n-value FSK modulation (n is 3 or over) on the basis of the received signal.
| JPS63107256 | CARRIER SYNCHRONIZING CIRCUIT |
| JP7423147 | wireless receiving device |
| JPH07202764 | DATA RESTORATION TECHNOLOGY THAT AVOIDS ILLEGALITY CONVERGENCE STATE |
YOSHIKAWA YOSHISHIGE
| JPH08237314A | 1996-09-13 | |||
| JPH10145442A | 1998-05-29 | |||
| JP2003152814A | 2003-05-23 |
Tomoyasu Sakaguchi
Hiroki Naito