Title:
RECEIVER
Document Type and Number:
Japanese Patent JP3737314
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce the scale of hardware without deterioration in an error rate characteristics of a receiver that conducts maximum ratio synthesis diversity.
SOLUTION: Dividers 110, 111 divide a compensation coefficient of each branch by a sum of all branches of level information of each reception signal. Multipliers 114, 115 multiply each output of the dividers 110, 111 with the received signal from each branch. An adder 116 sums outputs of the multipliers 114, 115 to conduct phase compensation, amplitude compensation and maximum ratio synthesis at the same time.
More Like This:
Inventors:
Hiroaki Sudo
Application Number:
JP12309199A
Publication Date:
January 18, 2006
Filing Date:
April 28, 1999
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H04B7/08; H04J11/00; H04B7/26; H04L1/06; (IPC1-7): H04B7/08; H04B7/26; H04J11/00; H04L1/06
Domestic Patent References:
| JP9284191A | ||||
| JP8195705A | ||||
| JP9018399A | ||||
| JP10233756A | ||||
| JP7307724A | ||||
| JP10322320A | ||||
| JP10126323A |
Attorney, Agent or Firm:
Koichi Washida