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Patent Searching and Data


Title:
RECEIVER
Document Type and Number:
Japanese Patent JPH10290182
Kind Code:
A
Abstract:

To provide the receiver that improves a transmission capacity by reducing inter-code interference given by a frequency switching noise onto demodulated data and reducing number of guard bits.

A timing correction circuit 11 measures in advance a circuit delay time of a high frequency tracking filter in a high frequency amplifier circuit 2, an intermediate frequency filter 5 and a base band filter 8, generates a frequency switching timing signal 11 to be corrected so as to increase the switching timing by the measured delay time and selects the high frequency circuit 2 and the local signal generating circuit 3. Since the inter-code interference due to frequency switching noise is contained within one symbol caused in an output demodulation waveform of a demodulation circuit 7 is contained within one symbol from a switching point, the guard bit length is reduced and the transmission capacity is improved.


Inventors:
UKEGAWA YUTAKA
Application Number:
JP9707397A
Publication Date:
October 27, 1998
Filing Date:
April 15, 1997
Export Citation:
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Assignee:
NEC CORP
International Classes:
H04B1/713; H04B1/7136; H04L7/00; (IPC1-7): H04B1/713
Attorney, Agent or Firm:
Matsuura