PURPOSE: To reduce the probability of inoperation, by utilizing that an output is reduced surely to a failure signal with 12-bit at the 12-bit code detecting system, correcting 1-bit error, in case of 1-bit error.

CONSTITUTION: A decoding circuit 2 performs code detection with the newest 12-bit signal train at each input of 1-bit and outputs either of corresponding signals S0, S1, and S2, which are stored. On the other hand, codes except code signals P0, P1, P2 are inputted, then a failure signal Sx is outputted. A control circuit 6 holds a signal Sx to a preceding value, by outputting a signal 6a to a memory circuit 5. When the failure signal is consecutive for 13-bit, the signal Sx is outputted via a circuit 4 and the signal 6a is released. In case of 1-bit error, an output signal has the preceding value and no signal Sx is outputted. In case of the error ≥2-bit, the signal S is outputted. Thus, the 1-bit error correction/2-bit error detection are executed to the error on the transmission line, allowing to decrease the rate of inoperation.