PURPOSE: To make the investigation of data by every byte by a CPU unnecessary, and to realize the fast transfer of the data, by detecting a control character stipulated by a synchronous communication system in DMA transfer, and informing it to the CPU.

CONSTITUTION: Synchronization between a control block and a data block sent from a serial line to a receiver is taken by a communication control LSI13, and a SYN character is removed. Afterwards, the block is changed to a reception data, and is transferred byte by byte to a memory 2 by a DMAC4. During the above DMAC transfer, the data at a time when a DACK signal to the LSI13 becomes active is detected at a control character detection circuit CRWD6 via a data bus 12. An interruption signal is generated when the data is the control character stipulated at the CRWD6, and it is informed to the CPU1 via a signal line 21, an interruption controller INTC5, and a signal line 24. And the CPU1 finds a transfer opposite address while executing an interruption processing, and processes the data with a stipulated communication procedure.