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Title:
RECEIVING CIRCUIT, AND SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM PROVIDED WITH THE SAME
Document Type and Number:
Japanese Patent JP2012156660
Kind Code:
A
Abstract:

To provide a receiving circuit which amplifies a high-speed signal more than a low-speed signal and suppresses power consumption, and to provide a semiconductor device and an information processing system provided with the same.

The receiving circuit, and the semiconductor device and the information processing system provided with the same according to the present invention comprise a first amplifier and a second amplifier having a cutoff frequency lower than that of the first amplifier. A received signal is inputted to the first amplifier and the second amplifier, and an output of the second amplifier is subtracted from an output of the first amplifier to output a resultant signal.


Inventors:
USHIO YUSHI
HAMANO DAISUKE
USUKINU TATSUNORI
Application Number:
JP2011012475A
Publication Date:
August 16, 2012
Filing Date:
January 25, 2011
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H03F3/68; H03F3/34; H03F3/45; H04L25/02
Attorney, Agent or Firm:
Manabu Inoue
Yuji Toda
Shigemi Iwasaki



 
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