RECEIVING CIRCUIT - Matsushita Electric Industrial Co., Ltd

Title:

RECEIVING CIRCUIT

Document Type and Number:

Japanese Patent JP3657377

Kind Code:

B2

Abstract:

PROBLEM TO BE SOLVED: To provide a receiving circuit whereby superior reception signal strength stability is obtained.
SOLUTION: The circuit is provided with a first antenna 1 and the second antenna 2 and also provided with means 10 and 11 generating a sum signal or a difference signal from two-groups of signals which are received by the respective antennas, the means 12 executing delay in one of the outputs of the sum signal or difference signal generating means 10 and 11, the means adding and synthesizing the output of the delay means 12 to and with the signal of a group without delay, a desired wave pass filter means 14 receiving the output of the adding and synthesizing means 13, a dividing means receiving the output of the desired wave pass filter means 14, orthogonal detection means 16-19 receiving the output of the dividing means 15 and filter means 20 and 21 receiving the outputs of the orthogonal detection means 16-19 and extracting a baseband signal. Then, a reception system after the adding and synthesizing means 13 is made to be one group so that miniaturization and low power consumption are attained.

Inventors:

Genichiro Ota
Kazunori Inokai
Sasaki Fujio
Hiroaki Sudo

Application Number:

JP35674896A

Publication Date:

June 08, 2005

Filing Date:

December 27, 1996

Export Citation:

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