Title:
RECEIVING OVERRUN CONTROL CIRCUIT
Document Type and Number:
Japanese Patent JP2948714
Kind Code:
B2
Abstract:
PURPOSE: To prevent the generation of data omission and to make it possible to read out data at any timing by outputting an overrun signal at the time of inputting an external writing signal prior to the end of transfer of receiving data to a data processing circuit.
CONSTITUTION: This receiving overrun control circuit is constituted of d type flip flops(FFs) 16 to 22 for fetching an input signal applied to a D input at the leading edge of a CK input and outputting the signal to a Q output, AND gates 23, 25 to 27, an inverter 24, and a NAND gate 28. The NAND gate 28 outputs an internal write signal 4 and a clock signal for a d type FF 21 based upon an external write signal 2 and an RX ready signal (signal indicating no end of transfer to the succeeding data processing circuit) 5 to be the Q output of the FF 21 is turned to low based upon the input of the clock signal. If the signal 5 is low at the time of inputting the signal 2, an overrun signal is outputted.
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Inventors:
SHIMAZAKI IKUO
Application Number:
JP8335893A
Publication Date:
September 13, 1999
Filing Date:
April 09, 1993
Export Citation:
Assignee:
SHAAPU KK
International Classes:
G06F13/00; G06F13/38; (IPC1-7): G06F13/00; G06F13/38
Attorney, Agent or Firm:
Takaya Koike