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Title:
CAPACITOR ARRAY DEVICE
Document Type and Number:
Japanese Patent JPH0722279
Kind Code:
A
Abstract:

PURPOSE: To lower residual inductance by providing an outer ground electrode at least on the surface or the rear of a device and electrically connecting the outer ground electrode with an inner ground electrode through a via hole.

CONSTITUTION: The capacitor array device 1 comprises a dielectric sheet 2a provided with a ground electrode 5a on the upper surface thereof, a dielectric sheet 2b provided with an inner ground conductor 6a on the upper surface thereof, a dielectric sheet 2c provided with inner signal conductors 7a, 7b, 7c on the upper surface thereof, and a dielectric sheet 2d provided with inner and outer ground electrodes 6b, 5b, respectively, on the upper and lower surfaces thereof. The dielectric sheets 2a, 2d are provided with via holes 8a, 8b. When the dielectric sheets are laminated, the outer electrode 5a is connected electrically with the inner conductor 6a through the via hole 8a and the outer electrode 5b is connected electrically with the inner conductor 6b through the via hole 8b.


Inventors:
OKUBO AKIRA
Application Number:
JP16487293A
Publication Date:
January 24, 1995
Filing Date:
July 02, 1993
Export Citation:
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Assignee:
MURATA MANUFACTURING CO
International Classes:
H01G4/232; H01G4/38; H03H7/075; (IPC1-7): H01G4/38; H01G4/232
Attorney, Agent or Firm:
Morishita Takeichi



 
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