PURPOSE: To receive surely a data signal from a data reception circuit even if a delay of the output timing of a data signal from a converter by using a signal delaying the output signal of a clock transmission circuit for a prescribed time as the reference to control the discriminating timing of a received data in a data reception circuit.
CONSTITUTION: When the number of converters connected to a clock signal line lc is increased and a clock voltage at an output terminal of a buffer 2 is expressed as VCO', since a PCM data signal VPC" inputted to a data reception circuit 4, starts the operation of the data reception circuit 4 after a delay time TD after a clock signal voltage VCO' reaches a threshold value because a delay circuit 5 inputs the clock signal VCO', that is at a time tGB' (tCB'>tGA'). Since the delay operation of the delay circuit 5 is conducted by using a clock signal of the clock signal line lc as the reference, even if the delay in the output timing of converters A1∼An is large, it is corrected automatically and the signal reception from the converting circuit A1∼An at the reception circuit 4 is conducted surely.
JPH06291785 | RECEPTION METHOD FOR DIGITAL DATA |
WO/1994/023509 | DATA TRANSFER SYSTEM |
JPS62179250 | DATA SINK |
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