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Patent Searching and Data


Title:
RECEPTION DATA TIMING GENERATING SYSTEM
Document Type and Number:
Japanese Patent JPS6096050
Kind Code:
A
Abstract:

PURPOSE: To receive surely a data signal from a data reception circuit even if a delay of the output timing of a data signal from a converter by using a signal delaying the output signal of a clock transmission circuit for a prescribed time as the reference to control the discriminating timing of a received data in a data reception circuit.

CONSTITUTION: When the number of converters connected to a clock signal line lc is increased and a clock voltage at an output terminal of a buffer 2 is expressed as VCO', since a PCM data signal VPC" inputted to a data reception circuit 4, starts the operation of the data reception circuit 4 after a delay time TD after a clock signal voltage VCO' reaches a threshold value because a delay circuit 5 inputs the clock signal VCO', that is at a time tGB' (tCB'>tGA'). Since the delay operation of the delay circuit 5 is conducted by using a clock signal of the clock signal line lc as the reference, even if the delay in the output timing of converters A1∼An is large, it is corrected automatically and the signal reception from the converting circuit A1∼An at the reception circuit 4 is conducted surely.


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Inventors:
YAMAGUCHI TOMOO
Application Number:
JP20256683A
Publication Date:
May 29, 1985
Filing Date:
October 31, 1983
Export Citation:
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Assignee:
TOSHIBA KK
International Classes:
H04L25/40; H04L7/00; H04Q11/04; (IPC1-7): H04L25/03
Attorney, Agent or Firm:
Noriyuki Noriyuki