Title:
RECEPTION PHASE SYNCHRONIZING CIRCUIT
Document Type and Number:
Japanese Patent JP3412991
Kind Code:
B2
Abstract:
PURPOSE: To make the phase of a clock signal continuous independently of reception burst and to shift a reception data signal to select and output the data in the optimum phase position.
CONSTITUTION: A reception clock generation circuit 1 which generates a clock with the frequency which is N times as high as the clock frequency required for the reception timing, a frequency dividing circuit 3 which divides the frequency of this reception clock to obtain a reference clock for prescribed reception timing, and a reception data storage and output means which stores inputted reception data and shifts the phase by the clock of the reception clock generation circuit 1 to output it are provided. Further, a selector 4 which selects the output in a specific phase position from plural outputs having different phases of the reception data storage and output means and a control means which checks the change point of reception data from the output of the reception data storage and output means and gives such select signal to the selector 4 that the selector 4 selects the phase position preliminarily set correspondingly to the phase position to the reference clock of the checked change point are provided.
Inventors:
Eiji Maekawa
Hitoshi Tagami
Yasushi Matsumoto
Tadayoshi Kitayama
Hitoshi Tagami
Yasushi Matsumoto
Tadayoshi Kitayama
Application Number:
JP27563995A
Publication Date:
June 03, 2003
Filing Date:
October 24, 1995
Export Citation:
Assignee:
Mitsubishi Electric Corporation
Nippon Telegraph and Telephone Corporation
Nippon Telegraph and Telephone Corporation
International Classes:
H04L25/40; H04L7/00; H04L7/02; (IPC1-7): H04L7/02; H04L7/00; H04L25/40
Domestic Patent References:
| JP353629A | ||||
| JP575653A | ||||
| JP6224962A |
Attorney, Agent or Firm:
Kaneo Miyata (2 outside)