PURPOSE: To improve an interframe encoding characteristic by controlling the oscillation frequency of a encoding-side timing circuit using the difference between the timing information of an encoding-side timing circuit at the time when a synchronizing signal is read out from a buffer memory and the decoding- side timing information when receiving the signal.

CONSTITUTION: An encoder 11 writes the encoded data in the buffer memory 13, and writes, at the time t=0 when one frame ends, the synchronizing signal FS via a synthesizing circuit 19. In the mean time, when the code is read out from the buffer memory, and if the signal FS is detected by a detecting circuit 20, the state tS of the timing circuit is inserted from a gate 21. On the encoder 12-side, if the signal FS is detected by a detecting circuit 22, the information that follows is extracted as the tR. A subtracting circuit 23 subtracts from this tR the status t=tS of the timing circuit 17 on the decoder-side (tS-tR). This difference is latched by a latch circuit 24, compared with a constant value C in order to control a voltage controlled oscillator VCO25. As a result, a correct timing signal is reproduced, and an excellent interframe encoding characteristic is obtained.