Title:
再構成可能なセマンティックプロセッサ
Document Type and Number:
Japanese Patent JP4203023
Kind Code:
B2
Abstract:
Data processors and methods for their configuration and use are disclosed. As opposed to traditional von Neumann microprocessors, the disclosed processors are semantic processors-they parse an input stream and direct one or more semantic execution engines to execute code segments, depending on what is being parsed. For defined-structure input streams such as packet data streams, these semantic processors can be both economical and fast as compared to a von Neumann system. Several optional components can augment device operation. For instance, a machine context data interface relieves the semantic execution engines from managing physical memory, allows the orderly access to memory by multiple engines, and implements common access operations. Further, a simple von Neumann exception-processing unit can be attached to a semantic execution engine to execute more complicated, but infrequent or non-time-critical operations.
Inventors:
Sikhdar, Somsbura
Application Number:
JP2004567407A
Publication Date:
December 24, 2008
Filing Date:
November 12, 2003
Export Citation:
Assignee:
MISTLETOE TECHNOLOGIES, INC.
International Classes:
H04L12/56; G06F9/30; G06F15/16; G06F17/27; G06F
Other References:
Yaohan Chu et al.,A Top-down Parsing Co-Processor for Compilation,System Sciences 1989.VOL.I: Architecture Track, Proceedings of The Twenty-Second Annual Hawaii International Conference on Kailua-Kona HI,1989年 1月,pp.403-413
Attorney, Agent or Firm:
Kazuo Asahi
Tatsuya Masuda
Tatsuya Masuda
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