PURPOSE: To obtain a reproduced signal having reduced timing jitters, by extracting a clock signal after reseting only the recorded and reproduced clock signal having the reset timing interval set within a fixed range to the normal value.
CONSTITUTION: A reset pulse is gated with the output of a monostable multivibrator 3 to prevent that the reset pulse is supplied to a counter circuit 5 with a time interval smaller than a fixed value. This process can eliminate the effect of variations of a sudden reset timing. The circuit 5 is reset with the above- mentioned obtained reset pulse. The clock information of the output of the circuit 5 has no sudden change and is equal to the jitter information less in varying frequency component due to the traveling of a tape, etc. This jitter information is fed to a PLL circuit to obtain a reproduced signal having reduced timing jitters.
MATSUSHIMA KOUJI
SHIMEKI TAIJI
KATOU MISAO
