PURPOSE: To efficiently represent the head of a macroblock by arranging two block addresses in one sink block.

CONSTITUTION: To a framing and error correcting circuit, DC coefficient data are sent, and transmission area information and information of a selected quantizer are sent; and those data are developed in two dimensions and an error correction code is added. In this case, the data are arranged in respective frames. Namely, the two block addresses 54A and 54B are provided at the head of the data 53. Then DC data DC1-DC5 of fixed code length of one macroblock MB1 are arranged successively to said addresses. Further, variable- length frequency data AC0, AC1... of the one macroblock MB1 are arranged in the decreasing order of the frequencies. Thus, the two block address are provided and then the macroblock arranged in one sink block can be represented sufficiently.