Title:
直交クロック分周器
Document Type and Number:
Japanese Patent JP4560039
Kind Code:
B2
Abstract:
A divide-by-n process is effected via a scale-by-four/n process followed by a divide-by-four process. A quadrature input clock facilitates a scale-by-four/n process, via a clock-phase selection process. By incorporating a terminal divide-by-four process, quadrature output signals are easily provided. A divide-by-three quadrature divider effects the scale-by-4/n process via a selection of every third quadrature clock phase, and the quadrature output of the divide-by-four process provides the control signals to effect this every-third clock phase selection.
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Inventors:
Redman-White William
Application Number:
JP2006506361A
Publication Date:
October 13, 2010
Filing Date:
March 19, 2004
Export Citation:
Assignee:
NXP B.V.
International Classes:
H03K5/15; G06F1/06; H03K23/42; H03K23/68
Domestic Patent References:
| JP2005505979A | ||||
| JP2004201169A | ||||
| JP2003198522A | ||||
| JP7212225A | ||||
| JP2001292062A |
Foreign References:
| US20030020523 | ||||
| US5781054 |
Other References:
HILLOCK T H,IBM TECHNICAL DISCLOSURE BULLETIN,米国,IBM CORP,1978年 5月,V20 N12,P5214
J.Craninckx他,「A 1.75-GHz/3-V Dual-Modulus Divide-by-128/129 Prescaler in 0.7-μm CMOS」,IEEE JOURNAL OF SOLID-STATE CIRCUITS,米国,IEEE,1996年 7月,VOL.31, NO.7,890-897頁
J.Craninckx他,「A 1.75-GHz/3-V Dual-Modulus Divide-by-128/129 Prescaler in 0.7-μm CMOS」,IEEE JOURNAL OF SOLID-STATE CIRCUITS,米国,IEEE,1996年 7月,VOL.31, NO.7,890-897頁
Attorney, Agent or Firm:
Kenji Sugimura
Tatsuya Sawada
Tatsuya Sawada