Title:
REDUNDANCY CIRCUIT
Document Type and Number:
Japanese Patent JPH01143415
Kind Code:
A
Abstract:
PURPOSE: To prevent the entire chip from being 'killed' by the short-circuit of an external net by controlling the electrical state of the separator circuit output node of a circuit group not supplied with power through an electrical connection means and turning it to the same electrical state as the separator circuit output node of the circuit group supplied with the power. CONSTITUTION: A circuit node 129 for the circuit group 100A is connected to the circuit node 138 for the circuit group 100B by the electrical connection means 136. For separator circuits 140 and 142, the collectors and emitters are respectively connected between power supply lines 110 and 111 and both terminals of a second power supply voltage VEE, the bases are respectively connected through a resistor network to power supply sources 110 and 111 and the power is supplied at all times during an operation. Thus, even when the short-circuit is present in the signal line of the external circuit net connected to the output nodes 144 and 148, it is not propagated to the respective circuit nodes 129 and 138 through the separator circuits.
Inventors:
JIEEMUZU JIYOSEFU KAATEIN
JIYATSUKU AASAA DOORAA
JIYOOJI JIYON JIYOODEI
KENESU RUUISU REINAA
JIYATSUKU AASAA DOORAA
JIYOOJI JIYON JIYOODEI
KENESU RUUISU REINAA
Application Number:
JP20486888A
Publication Date:
June 06, 1989
Filing Date:
August 19, 1988
Export Citation:
Assignee:
IBM
International Classes:
G05B9/03; G06F11/20; G11C29/00; H03K19/003; H03K19/086; H03M7/00; (IPC1-7): G05B9/03; H03K19/003; H03M7/00
Attorney, Agent or Firm:
Jiro Yamamoto (1 person outside)