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Title:
REDUNDANT CIRCUIT
Document Type and Number:
Japanese Patent JPH01276496
Kind Code:
A
Abstract:

PURPOSE: To relieve the defective memory cell of another block with the redundant memory cell of a special certain block by controlling the output of a block selecting signal generating circuit with a selecting signal to the redundant memory cell of the prescribed block.

CONSTITUTION: The output of a block selecting signal generating circuit 20 is controlled by passing a redundant memory cell selecting signal of a decoder 19 for redundancy through an AND gate 21, an OR gate 22 and an inverter 23. When the selecting signal 18 is in a selecting condition 'H', a left block selecting signal 24 is forcibly caused to be non-selection and a right block selecting signal 25 goes to the selecting condition. At such a time, a redundant memory cell 17 is selected. When the selecting signal 18 is the 'L' of non- selection, the output of the block selecting signal generating circuit 20 is given to a decoder 12 as it is and the right or left block is selected. Thus, the redundant memory cell of a certain block is used also as the redundant memory cell for the other block and the defective memory cell of the other block can be also relieved.


Inventors:
ISHIBASHI KENJI
Application Number:
JP10574488A
Publication Date:
November 07, 1989
Filing Date:
April 27, 1988
Export Citation:
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Assignee:
SHARP KK
International Classes:
G11C29/00; G11C11/34; G11C11/401; G11C29/04; (IPC1-7): G11C11/34; G11C29/00
Domestic Patent References:
JP62153700B
Attorney, Agent or Firm:
Takeshi Sugiyama (1 outside)