Title:
REDUNDANT CONFIGURATION FOR NOISE SUPPRESSION OF ANALOG CIRCUIT
Document Type and Number:
Japanese Patent JP2015213314
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a noise suppression circuit for generating a noise reduction signal.SOLUTION: A noise suppression circuit 100 includes a plurality of functional blocks 110A, 110B to 110n configured to generate output signals 113A, 113B to 113n, respectively, a first extreme value determination unit 120 configured to determine an output signal having a signal value of first extreme value, out of the output signals from the plurality of functional blocks, and a processing unit 140 configured to determine the signal value of a noise reduction signal 145, by off-setting the signal value of the output signals from plurality of functional blocks. When determine the signal value of the noise reduction signal 145, the processing unit removes the first extreme value from the plurality of signal values.
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Inventors:
VOLKER LUECK
Application Number:
JP2015088821A
Publication Date:
November 26, 2015
Filing Date:
April 23, 2015
Export Citation:
Assignee:
TESAT SPACECOM GMBH & CO KG
International Classes:
H04B15/00; H04B1/74
Domestic Patent References:
| JPS512311A | 1976-01-09 |
Attorney, Agent or Firm:
Hideo Akazawa