PURPOSE: To prevent disturbance even with a small circuit scale by inputting an output pulse of a frequency divider to a 2nd phase comparator.
CONSTITUTION: An input clock pulse is inputted to a phase synchronizing circuit 10 and an output phase locked to a frequency divider 4 is inputted to a 2nd phase comparator 6. On the other hand, an output of a voltage controlled oscillator VCO 3 of the phase synchronization circuit 10 is inputted as a clock of a clock pulse generator 5 comprising counters and outputs a pulse having a window to a pulse of the same frequency as that of the input clock pulse and a 2nd phase comparator 6 receives the pulse. When an output pulse of the frequency divider 4 is not resident in the window, the count of the clock pulse generator 5 is reset to obtain a reference clock phase-locked with the input clock pulse. Thus, even when noise is superimposed on the output due to changeover or the like of a selector 22, it is absorbed by the phase synchronization circuit 10, the output of the frequency divider 4 is a clock pulse in phase-lock without noise and the circuit scale is reduced.
KAMOI NOBUHISA
IYOTA TOSHIO
YOSHINO TOYOHIKO
EISAKI HIDEKI
