PURPOSE: To simplify the structure and to reduce a failure rate by using an upper limit discrimination circuit, a lower limit discrimination circuit and a reference value generating circuit for a conventional reference value generating circuit as a reference value generating ROM and an upper/lower limit storage flip-flop.

CONSTITUTION: The reference value generating ROM 14 generating a reference signal 10, a quasi-upper limit reference signal 8 and a quasi-lower limit reference signal 9 based on a parallel signal 1, an upper limit reference signal 6 and a lower limit reference signal 7 and an upper/lower limit storage flip-flop 13 using the quasi-upper limit reference signal 8, the quasi-lower limit reference signal 9, a reference detection clock signal 4 and a reference clear signal 5 are provided to the circuit. Thus, a failure rate is reduced and the circuit in the design is simplified.