Title:
REFRESH CONTROL OF SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JP3726661
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a technique through which refresh operations suitable to a plurality of respective operating states a semiconductor memory can take are performed.
SOLUTION: In an operation cycle, a memory chip 200 starts a refresh operation in synchronism with an ATD signal that indicate a change in an address after the generation of a refresh timing signal RFTM. Moreover, in a snooze state (a low power consumption state), a refresh operation is started in accordance with the generation of the signal RFTM regardless of the presence or absence of the ATD signal.
Inventors:
Koichi Mizugaki
Application Number:
JP2000265063A
Publication Date:
December 14, 2005
Filing Date:
September 01, 2000
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
G11C7/10; G11C11/403; G11C11/406; (IPC1-7): G11C11/406; G11C11/403
Domestic Patent References:
| JP2001307485A | ||||
| JP2002074944A | ||||
| JP6036557A | ||||
| JP2002074945A |
Attorney, Agent or Firm:
Takao Igarashi
Takashi Shimoide
Hiroshi Ichikawa
Mitsuhiro Kato
Takashi Shimoide
Hiroshi Ichikawa
Mitsuhiro Kato
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