To provide a register device capable of reducing a delay time of a clock signal for high-speed operation and capable of restricting the power consumption and an influence of the noise even in the case of controlling a buffer and a clock skew.

An input single phase clock single CLK1 is converted to a double-phase clock signals CLK2 and XCLK2 in positive and negative having a small amplitude by a differential clock driver 3. A differential clock registor 4 provided with a built-in differential amplifier unit or arranged near the differential amplifier converts the double-phase clock signals CLK2 and XCLK2 to a single phase clock signal of the operating voltage by differentially increasing amplitude thereof. Amplitude and a delay time of the clock signal can be thereby reduced, and the clock signal can be supplied at a high speed, restricting the power consumption.