PURPOSE: To make it possible to execute a fixed point and a floating point computer processings by forming a separated pipeline structure with a register and logical operation units.

CONSTITUTION: A logical operation means 450 is provided with the parallel logical operation units 450a and 450b, and it executes the fixed point and the floating point operation processings in a data word in accordance with the output of a register file 444. Data word inputs 430, 431 and 432 are supplied to the drain input of the file 444 and the operation means 450 and a multiplexer MUX 442 selectively stores the data word in the file 444. MUX 446 and 448 transfer the output of the file 444 to the operation means 450. A logical operation limitter/shifter circuit 454 restricts and measures the data word of the output of the operation means 450.